AEC-Q100 PLL clock synthesizer for automotive timing trees
The CDCEL913IPWRQ1: It accepts either an LVCMOS reference or a crystal input and delivers three LVCMOS clock outputs from a single PLL core, with a maximum output frequency of 230 MHz. The PLL includes a bypass mode that passes the input reference directly to the outputs — useful for test modes or when the system needs a clean, unmultiplied clock during bring-up.
The 1.7V–1.9V supply range ties this part to low-voltage core domains. At 230 MHz max output, the CDCEL913IPWRQ1 covers common automotive clock frequencies. The 1:3 input-to-output ratio means a single reference can feed three clock domains without an external fan-out buffer.
Package and footprint — layout considerations
Surface-mount only — the Tape & Reel option (TR) is the standard production reel; Cut Tape (CT) is available for prototyping or small-batch builds.