230 MHz PLL clock generator with 1:9 fanout
The Texas Instruments CDCE949PWR is a 4-PLL VCXO clock generator that accepts an LVCMOS or crystal input and delivers up to nine LVCMOS outputs at frequencies up to 230 MHz. It integrates four PLLs with bypass capability, a divider chain, and a 1:9 input-to-output ratio — essentially a clock source and fanout buffer in one 24-TSSOP package. This part is aimed at systems that need multiple clean clock domains from a single reference: networking gear, base stations, test equipment, and FPGA-based designs where a single oscillator must feed several PLLs or clocked blocks.
If your board already has a 1.8 V rail, the CDCE949PWR can run directly from it without an extra regulator. A clean, low-noise 1.8 V supply is assumed; any ripple on that rail will appear on the output clocks as jitter.
It is not specified for automotive (no AEC-Q grade) or extended-temperature applications.