230 MHz PLL clock fanout in a 24-TSSOP
The integrated PLL supports frequency synthesis and jitter attenuation; a bypass mode lets the reference clock pass through unmodified when the PLL is not needed. It operates from a 1.7V to 1.9V supply rail, which ties it to the core voltage plane of low-power ASICs, FPGAs, or SoCs rather than a 3.3V or 2.5V I/O rail.
Supply rail and temperature grade — fit for industrial base stations
The 1.7V to 1.9V supply range is narrow and low — this part is designed for the core supply of a digital processor or FPGA, not a general-purpose 3.3V clock buffer.