PLL clock generator with bypass — what the 1:7 ratio buys you
The Texas Instruments CDCE937PWRG4 is a PLL clock generator that accepts either an LVCMOS or crystal reference and produces up to seven LVCMOS clock outputs, each programmable up to 230 MHz. The integrated PLL includes a bypass path — when bypassed, the input clock passes through with minimal added jitter, useful for system test modes or low-latency paths. The 1:7 input-to-output ratio means a single reference can feed multiple clock domains, reducing the external oscillator count on the board.
Supply rail and temperature — design constraints
The device operates from a 1.7V to 1.9V supply, which aligns with 1.8V logic families common in low-power FPGAs, SoCs, and memory interfaces. The 20-TSSOP package (4.40 mm width) is a fine-pitch surface-mount footprint; verify the land pattern matches the supplier device package drawing before layout.