PLL clock generator with bypass — 230 MHz ceiling
The CDCE937PWG4 is a PLL clock generator from Texas Instruments, part of the CDCE937 family, delivering up to 230 MHz on the output with a 1:7 input-to-output ratio. It integrates a PLL with bypass mode, so you can clean up a jittery reference or pass a clean clock straight through without the loop filter in the way — handy when a system needs both a synthesized clock and a direct feed from a crystal.
Supply rails and temp grade — fits 1.8V-core designs
Input accepts LVCMOS or a crystal; output is LVCMOS, non-differential. That means it mates cleanly with standard CMOS logic inputs without level translation, but it is not suited for differential clocking like LVPECL or LVDS — keep that in mind if the downstream receiver expects a pair.
20-TSSOP — field-swappable with basic kit
No differential routing needed, so a two-layer board with a solid ground pour handles the layout.