The CDCE925PW is a single-circuit PLL clock generator from Texas Instruments that takes an LVCMOS or crystal input and produces up to five LVCMOS outputs at frequencies up to 230 MHz. It operates from a 1.7V to 1.9V supply rail, which is tighter than the common 3.3V or 2.5V clock-generator voltages. That narrow window means the board needs a dedicated LDO or low-noise regulator — the same rail that powers the core of a 1.8V FPGA or SoC is a natural source. It does not extend to under-hood automotive or downhole drilling — those would need an AEC-Q100 or extended-range part.
Because the supply is 1.7V–1.9V, the LVCMOS output swing is rail-limited. If the downstream load expects a 3.3V logic threshold, a level translator or a different clock generator is needed. The CDCE925PW is designed for 1.8V logic domains. The PLL includes a bypass mode, which lets the input clock pass through to the outputs without multiplication. That is useful during system debug or when the PLL must be disabled without losing the clock to the rest of the board.
Active status and procurement posture
No stock-holding claim is made — the part is sourced per RFQ through our multi-supplier network.