230 MHz spread-spectrum clock with PLL bypass
The PLL includes a bypass path, so you can feed through a clean clock when spreading is not needed. Maximum output frequency is 230 MHz, which covers most microcontroller, FPGA, and serial-link reference clock requirements.
The 14-TSSOP package (4.40 mm wide) is a common footprint with 0.65 mm pitch — fine for hand-assembly rework but needs a solid ground pour under the PLL analog section to keep jitter low. The 1:3 fanout ratio means one input drives three clock outputs, which saves a separate fanout buffer on the BOM.
