PLL frequency synthesizer with 1:6 fan-out
The Texas Instruments CDCE906PW is a PLL frequency synthesizer that accepts LVCMOS or crystal inputs and delivers six LVCMOS outputs, each programmable up to 167 MHz. The integrated PLL includes a bypass mode, letting the designer pass a clean reference clock straight through when synthesis is not needed.
167 MHz ceiling and 1:6 ratio — clock tree planning
The 167 MHz maximum output frequency covers most common system clocks — Ethernet MACs, FPGAs, SoC reference inputs — without needing a higher-speed PLL. The 1:6 input-to-output ratio means a single reference oscillator can feed six clock domains, reducing BOM oscillator count and board area.
Runs from 3.0 V to 3.6 V, matching the 3.3 V rail common in digital systems.
Housed in a 20-TSSOP (4.40 mm width) surface-mount package. The 0.65 mm pitch is layout-friendly on two-layer boards; the small body saves space on dense mixed-signal cards.