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Texas Instruments CDCE72010RGCR — Clock & Timing ICs

CDCE72010RGCR Clock Jitter Cleaner, 1.5 GHz, 3:20 Fanout

MPNCDCE72010RGCR
Active

Texas Instruments CDCE72010RGCR, Clock Synchronizer / Fanout (Distribution) / Jitter Cleaner, PLL Yes, 3:20 Input:Output, 1.5 GHz max, LVCMOS/LVDS/LVPECL I/O, 64-VQFN (9x9), -40°C to 85°C.

$12.9960Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CDCE72010RGCR specifications
ParameterValue
TypeClock Synchronizer, Fanout (Distribution), Jitter Cleaner
MountingSurface Mount
Voltage3V ~ 3.6V
Frequency1.5GHz
Operating temperature-40°C~85°C
PLLYes
InputLVCMOS, LVDS, LVPECL
OutputLVCMOS, LVDS, LVPECL
PackageTape & Reel (TR)
Case64-VFQFN Exposed Pad
Divider (Multiplier)Yes/No
Number of circuits1
Ratio - Input:Output3:20
Differential - Input:OutputYes/Yes

Product details

1.5 GHz jitter cleaner with 20-output fanout

The Texas Instruments CDCE72010RGCR is a clock synchronizer, jitter cleaner, and fanout distribution device in a single 64-VQFN (9x9) package. It accepts LVCMOS, LVDS, or LVPECL reference inputs and delivers up to 20 cleaned, synchronized clock outputs at frequencies up to 1.5 GHz, also in LVCMOS, LVDS, or LVPECL formats.

Fanout ratio and differential paths

The 3:20 input-to-output ratio means three independent reference inputs can be selected and fanned out to twenty outputs. Both input and output paths support differential signaling, which preserves signal integrity over the VQFN-to-board traces at multi-GHz edge rates. The internal PLL (listed as Yes) performs jitter cleaning on the selected reference, reducing phase noise before the signal is distributed.

No last-time-buy or end-of-life notification is on file.

Frequently asked questions

What is the CDCE72010RGCR used for?

It synchronizes, cleans jitter from, and fans out clock references in high-speed digital systems. Typical applications include wireless infrastructure base stations, data converters (ADC/DAC clocking), FPGA reference clock trees, and networking equipment where multiple clean clocks at up to 1.5 GHz are needed.