Six unbuffered inverters for mixed-voltage signal conditioning
The CD4069UBMT packs six independent inverter gates in a single 14-SOIC package, each with one input. Unbuffered output means the propagation delay varies with supply — at 15 V into a 50 pF load the max delay is 50 ns, which sets the usable toggle rate in a mixed 5 V / 12 V logic chain. Supply range spans 3 V to 18 V, so the same part interfaces a 3.3 V microcontroller output to a 12 V relay driver without a level translator. The input logic thresholds scale with VDD: low at 1 V to 2.5 V, high at 4 V to 12.5 V.
Temperature grade and quiescent budget
Quiescent current maxes at 1 µA across the full range, so the battery-powered logic chain draws negligible idle current. Output drive is symmetric at 3.4 mA source and sink, enough to switch a standard CMOS input or a small-signal MOSFET gate directly. The 14-SOIC footprint (3.90 mm body width) suits compact mixed-signal boards where a DIP-14 would consume too much real estate.