RXv3 core at 120 MHz with 512 KB Flash
The R5F56604DGFP#30 runs a 32-bit RXv3 core at 120 MHz, with 512 KB of on-chip Flash program memory and 128 KB of SRAM — enough headroom for a real-time control loop with a moderate protocol stack, leaving room for the application logic after the HAL and RTOS footprint. An integrated 32 KB EEPROM block stores calibration constants and fault logs without needing an external serial EEPROM — one fewer part on the BOM and one fewer I²C or SPI bus slot consumed.
Analog integration and peripheral set
Twenty-four 12-bit ADC channels and two 12-bit DAC channels are on-chip — a sensor-heavy design like a multi-channel data logger or a motor-control board with current-sense feedback can sample all phases without external multiplexing. The peripheral list includes DMA, LVD, POR, PWM, and WDT — the LVD and POR handle brown-out and power-on sequencing internally, so the supply supervisor on the board can be a simple reset IC rather than a full sequencer. Connectivity covers CANbus, EBI/EMI, I²C, LINbus, SCI, and SPI — the CAN and LIN interfaces suit industrial automation and automotive-adjacent control nodes; the EBI/EMI bus can expand memory or connect an FPGA without bit-banging GPIO.
Package and board-fit
Housed in a 100-LQFP with a 14x14 mm body (supplier device package 100-LFQFP), the 89 I/O lines fan out from the four sides — a four-layer board with a ground plane under the core is the practical minimum for signal integrity at 120 MHz, though a two-layer layout can work with careful routing on the slower peripherals.
No stock-holding claim — quoted to order.