Zener ESD clamp for 3.3V signal lines
Its 3.3V (Max) reverse standoff voltage sits just above the nominal supply, so it stays invisible during normal operation and only conducts when a spike exceeds the 5V breakdown threshold. With a clamping voltage of 11.5V at 2A (8/20µs pulse), it limits the peak voltage seen by the protected IC to a level that most 3.3V CMOS I/O cells survive. The 15pF capacitance at 1MHz is low enough to avoid degrading edge rates on USB 2.0 (480 Mbps) or similar high-speed differential pairs.
SOD-923 footprint and reflow profile
The SOD-923 package is small, so the PCB land pattern needs tight solder-paste registration. The single bidirectional channel means only two pads: one for the signal line, one for ground. No power-line protection; this part is for signal-line clamping only. The small thermal mass means the part heats up quickly during a pulse, but the 2A peak pulse current rating (8/20µs) is sufficient for ESD strikes.
onsemi lists the ESD9B3.3ST5G as Active.