Tri-Core architecture and speed split
The SPC5748GSK1MMJ6: Three 32-bit e200z cores — two e200z4 and one e200z2 — run at 80 MHz or 160 MHz, depending on the core and application demand. The e200z4 cores handle the main compute and real-time loops; the smaller e200z2 can run a safety monitor or communication stack without stealing cycles from the primary tasks. This asymmetric multi-processing architecture is typical for domain controllers that need one core dedicated to lockstep safety logic (ISO 26262 ASIL-D capable) while the other runs application code.
Memory map — 6 MB flash, 768 KB SRAM
6 MB of on-chip flash (6M x 8) and 768 KB of SRAM (768K x 8) give the SPC5748GSK1MMJ6 room for a full AUTOSAR stack, application code, and data buffers without external memory in many designs. The flash is large enough to hold multiple boot images or an over-the-air update staging area, which matters for connected automotive and industrial gateways.
Connectivity and peripheral set for gateway roles
CANbus, Ethernet, USB (with OTG), I2C, LIN, SAI, and SPI are all on-die — the part can bridge a vehicle CAN backbone to an Ethernet backbone and serve as a telematics gateway without external PHY management beyond the transceivers. 178 I/O lines in the 256-MAPPBGA package provide enough pins to interface multiple sensor arrays, actuators, and display panels simultaneously.
ADC array and analog front-end
The data converter subsystem includes 80 channels of 10-bit ADC and 64 channels of 12-bit ADC, enough to sample multiple analog sensors (temperature, pressure, position) without external multiplexing.