I²C bus buffer in an 8-pin SOIC
The NXP PCA9517D,118 is a 2-channel Buffer, ReDriver for 2-Wire Bus (I²C) applications, operating at a maximum data rate of 400 kHz. It sits between a master and a segmented bus segment, regenerating the clock and data signals to extend the physical reach beyond the standard 400 pF capacitance limit.
400 kHz standard-mode, 2-channel buffering
Two bidirectional channels mean the PCA9517D,118 buffers both SDA and SCL lines. The 400 kHz ceiling is the standard-mode I²C limit — if your bus runs at 100 kHz or 400 kHz, this part fits; for fast-mode Plus (1 MHz), look elsewhere in the NXP I²C buffer family. Supply current is 5 mA typical, and input capacitance is 6 pF per pin — low enough that the buffer itself does not eat a significant chunk of the bus capacitance budget.
Active lifecycle, ROHS3, no obsolescence flag
For BOM risk management, the 8-SOIC package is a widely second-sourced footprint. If a shortage hits, functionally equivalent I²C buffers from other vendors in the same package can be evaluated — but no pin-compatible direct replacement from NXP is listed on this record.