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NXP Semiconductors MCIMX6X2EVN10ABR — Microcontrollers & Processors (MCU / MPU / DSP)

NXP MCIMX6X2EVN10ABR i.MX6SX MPU

MPNMCIMX6X2EVN10ABR
End of Life

NXP i.MX6SX series, MCIMX6X2EVN10ABR, dual-core ARM Cortex-A9 1 GHz / Cortex-M4 227 MHz, 2 Core 32-Bit, LPDDR2/LVDDR3/DDR3, dual GbE, USB 2.0 + PHY, -20 to 105°C, 400-MAPBGA (17x17), ROHS3.

$38.1Ref. price · indicative, final on quote
Packaging400-LFBGA
RoHSROHS3 Compliant
Seriesi.MX6SX
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

MCIMX6X2EVN10ABR specifications
ParameterValue
Seriesi.MX6SX
MountingSurface Mount
Voltage - i (O)1.8V, 2.5V, 2.8V, 3.15V
Additional interfacesAC'97, CAN, I²C, I²S, MMC/SD/SDIO, PCIe, SAI, SPDIF, SPI, SSI, UART
Display & interface controllersKeypad, LCD
Operating temperature-20°C ~ 105°C (TJ)
Number of cores (Bus width)2 Core, 32-Bit
USBUSB 2.0 + PHY (1), USB 2.0 OTG + PHY (2)
Speed227MHz, 1GHz
PackageTape & Reel (TR); Cut Tape (CT)
Ethernet10/100/1000Mbps (2)
Core processorARM® Cortex®-A9, ARM® Cortex®-M4
Case400-LFBGA
RAM controllersLPDDR2, LVDDR3, DDR3
Co-Processors (DSP)Multimedia; NEON™ MPE
Security featuresA-HAB, ARM TZ, CAAM, CSU, SNVS, System JTAG, TVDECODE
Graphics accelerationYes

Product details

Dual-core asymmetric processing in a single BGA

The NXP MCIMX6X2EVN10ABR from the i.MX6SX series is a heterogeneous dual-core processor that pairs a 1 GHz ARM Cortex-A9 application core with a 227 MHz ARM Cortex-M4 real-time core in a 400-MAPBGA package (17x17 mm). The A9 runs a Linux or Android stack for HMI and networking, while the M4 handles deterministic control loops, motor commutation, or sensor fusion — no separate microcontroller needed on the board. The asymmetric multiprocessing (AMP) architecture lets each core access shared peripherals like the dual 10/100/1000 Mbps Ethernet MACs and the USB 2.0 host and OTG ports with integrated PHY.

Memory and I/O headroom for industrial system integration

The memory controller supports LPDDR2, LVDDR3, and DDR3, giving the system architect flexibility to match cost vs. bandwidth targets — LPDDR2 for low-power portable terminals, DDR3 for cost-optimized fixed equipment. The peripheral set includes CAN, I²C, I²S, SAI, SPDIF, SSI, UART, MMC/SD/SDIO, PCIe, and AC'97, covering most industrial communication, audio, and storage interfaces without external bridge chips. The integrated graphics acceleration and LCD/keypad controllers support a local display for operator panels.

Industrial temperature grade and security features

The security subsystem includes A-HAB, ARM TrustZone, CAAM, CSU, SNVS, System JTAG, and TVDECODE — enabling secure boot, encrypted storage, and tamper detection for metering or payment terminals.

Frequently asked questions

Does MCIMX6X2EVN10ABR support Linux BSP?

Yes, as a Cortex-A9 device in the i.MX6 series, it is supported by NXP's Linux BSP and Yocto Project layers. The Cortex-M4 core runs bare-metal or FreeRTOS.

What are the USB interfaces on MCIMX6X2EVN10ABR?

It provides one USB 2.0 host port with integrated PHY and one USB 2.0 OTG port with integrated PHY, eliminating external transceiver ICs.

What is the difference between MCIMX6X2EVN10ABR and MCIMX6X2EVN10AB?

The suffix 'R' indicates tape-and-reel packaging for automated assembly. The 'AB' variant typically ships in trays. Electrically and functionally they are identical.