17 ns propagation delay – bus timing anchor
For a bus-coupled system running at 10–20 MHz, that 17 ns window sets the setup-and-hold budget on the downstream register — every gate, trace, and connector adds to that margin before the clock edge arrives.
Tri-state bus isolation and output drive
Tri-state outputs allow the latch to release the bus when the output-enable control is deasserted, preventing driver contention on a shared data line. The output stage can source or sink 6 mA per channel, sufficient to drive a single LSTTL load or a short PCB trace directly.