55 MHz clock and 35 ns propagation delay
The 55 MHz maximum clock frequency sets the upper counting or data-shifting rate for a synchronous design. The 35 ns max propagation delay (measured at 6 V supply and 50 pF load) means this part fits moderate-speed control and interface logic.
Supplied in a 16-pin SOIC package with 3.90 mm body width (supplier device package 16-SO). Surface-mount assembly compatible with standard reflow profiles.
Nexperia continues to manufacture this part, so there is no last-time-buy pressure.
