The 74ALVCH16374DL,118 is a dual 8-bit D-type flip-flop from NXP's 74ALVCH family — 16 flip-flops in one 48-pin SSOP package, each triggered on the positive clock edge. The outputs are tri-state and non-inverted, so you can bus them onto a shared data line without contention. Clock frequency hits 350 MHz, which puts it in the fast-logic lane for memory interfaces, FIFO buffers, and high-speed register files. The 3.4 ns propagation delay at 3.3V and 50 pF load is the number to plug into your timing spreadsheet. Supply voltage spans 1.2V to 3.6V, so this part can sit on a 1.8V or 2.5V rail and still talk to 3.3V logic on the other side of the bus. The 24 mA output drive handles a fan-out of several loads before the edge slows down.
Housed in a 48-BSSOP package with 0.295-inch body width and 7.50 mm footprint. The supplier device package is 48-SSOP — same mechanical outline, different naming convention. The 0.65 mm pitch is fine-pitch enough that a two-layer board can route it, but a four-layer board gives cleaner power delivery for the 350 MHz clock edge. The 5 pF input capacitance is low enough that the clock line won't load down the previous stage.
Sourced to order against BOM quantities.