Key interfaces and memory support
Display and camera pipeline
On-chip display and interface controllers support eDP, HDMI, MIPI-DSI, and MIPI-CSI. Graphics acceleration offloads UI rendering from the Cortex-A53 cores.
Security and co-processor architecture
Security features include ARM TrustZone, CAAM, HAB, RDC, RTC, SJC, and SNVS. The Cortex-M4 co-processor runs independently for low-latency control tasks.
Package and thermal environment
Supplied in a 621-ball FCPBGA package measuring 17x17 mm, surface-mount.
Product status is Active, and the part is ROHS3 compliant.