180 MHz Cortex-M3 with ROMless external-flash architecture
The ROMless architecture means all code executes from external Flash or SRAM via the EBI/EMI interface — a deliberate choice for systems where firmware size exceeds internal Flash limits or where the memory map must be shared with an FPGA or application processor. The 136K x 8 of on-chip RAM handles data buffers and stack; the rest of the memory budget is on the board.
CANbus and industrial connectivity
The peripheral set also includes I²C, SPI, SSI, SSP, UART/USART, IrDA, Microwire, MMC/SD, and EBI/EMI — enough serial and parallel bandwidth to bridge a CAN bus to a local display, an SD card logger, or a sensor array. The 83 general-purpose I/O lines leave room for local control and status monitoring without an external GPIO expander.
