NXP LPC17xx series ARM Cortex-M3 MCU, order code LPC1766FBD100K; 100MHz clock, 256KB Flash, 64KB SRAM; 70 I/O, Ethernet, USB OTG, CAN, SPI/I²C/USART; 2.4–3.6V single rail; -40°C–85°C; 100-LQFP (14×14mm) surface-mount package.
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Specifications
| Parameter | Value |
|---|---|
| Series | LPC17xx |
| Mounting type | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 2.4V ~ 3.6V |
| Operating temperature | -40°C~85°C(TA) |
| Speed | 100MHz |
| Package | Bulk |
| RAM size | 64K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT |
| Connectivity | CANbus, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG |
| Number of i (O) | 70 |
| Core processor | ARM® Cortex®-M3 |
| Case | 100-LQFP |
| Data converters | A/D 8x12b; D/A 1x10b |
| Program memory size | 256KB (256K x 8) |
Frequently asked questions
Is the LPC1766FBD100K still active or has NXP moved it to discontinued?
Active, ROHS3 compliant. No last-time-buy or PCN flag is present in the current record.
Is there a drop-in compatible or second-source MCU with the same 100-LQFP footprint and flash density?
The same-function sibling in the LPC17xx family with a higher flash density is the LPC1768 — it shares the 100-LQFP package, 100MHz Cortex-M3 core, and 70-I/O footprint but doubles the Flash to 512KB, giving headroom for firmware images that approach the 256KB ceiling on the LPC1766. If the design requires a pin-compatible alternate with more memory, the LPC1768 is the validated family cross-reference. No officially designated second-source alternate outside the NXP LPC17xx family is present in the current record.
Does the 64KB SRAM allow simultaneous TCP/IP stack, USB OTG buffers, and motor control PWM table in one firmware image?
The 64KB SRAM figure is on-chip. Whether it accommodates simultaneous TCP/IP stack, USB OTG DMA buffers, and motor control PWM lookup tables depends on the firmware footprint and which RTOS or bare-metal allocator is used — the silicon provides the resource; the firmware engineer allocates it. Designs approaching the SRAM ceiling should confirm their stack/buffer sizing against the 64KB figure before BOM lock.