120 MHz — what it buys you on the bus
The 120 MHz core clock is the headline number, but the real throughput comes from the multi-layer AHB bus matrix and the DMA controller. A TCP/IP stack with Ethernet and USB active simultaneously will still leave MIPS for a control loop at a few kilohertz. The 512 KB Flash is split into sectors for wear-leveled field updates over CAN or Ethernet — useful when the device is in a sealed enclosure and firmware comes over the wire. The 96 KB SRAM is tight for a full Ethernet buffer plus a large display frame; plan to use the external bus interface if you need more than a QVGA buffer.
Lifecycle status is Active — NXP continues to manufacture this part, so no last-time-buy pressure. The LPC1778 family is well-established with a long production tail; no official successor has been announced.