100 MHz MEMS oscillator for PCIe clock trees
Its HCSL output is the native clock format for PCIe Gen 1/2/3 and many high-speed SERDES interfaces — no external level translation needed when feeding a PCIe switch or FPGA transceiver bank. The ±20 ppm frequency stability holds the reference tight enough for 1000BASE-T Ethernet and SATA III without a separate VCXO or PLL cleanup loop.
The supply voltage range of 2.5V to 3.3V lets it run from a common 3.3V rail or a lower 2.5V FPGA bank without a separate regulator — the internal LDO cleans the rail noise before it reaches the MEMS element.