MEMS oscillator with HCSL output for PCIe clocking
Output is HCSL (High-Speed Current Steering Logic), the differential signalling standard for PCIe reference clocks — a 100 MHz HCSL output directly drives the REFCLK pair on a PCIe root complex or switch without external level translation. Supply voltage range is 2.5V to 3.3V, covering the common 2.5V and 3.3V rails on networking and computing boards — the Enable/Disable function lets the system gate the clock during low-power sleep states.
Housed in a 6-VDFN package measuring 2.50mm x 2.00mm with a seated height of 0.90mm — the small footprint fits dense PCB layouts, but the 6-pin VDFN requires a solder-paste stencil aperture matched to the exposed pad for reliable reflow. Frequency stability is ±20ppm over the full temperature range — tight enough for most 100 MHz system clocks, though a PCIe Gen3 or Gen4 reference clock typically requires ±100ppm or better, so this part meets that margin comfortably.