100 MHz HCSL reference clock for PCIe and high-speed interfaces
The DSC1224BL2-100M0000T is a 100 MHz MEMS-based XO with HCSL output, designed to serve as a reference clock for PCIe Gen1/2/3, Ethernet, and FPGA transceiver blocks. The HCSL (High-Speed Current Steering Logic) output provides the differential swing and common-mode levels required by PCIe without external termination resistors — the receiver's 50 Ω to ground on each leg sets the bias.
Supply flexibility and enable/disable control
The 2.5V to 3.3V supply range lets the same part serve 2.5V and 3.3V logic domains — no separate voltage variant or external LDO needed when moving between FPGA banks or switching to a lower-voltage SoC.