100 MHz LVDS clock source for high-speed signal chains
LVDS output delivers the low-jitter differential signaling needed for high-speed serial links, FPGA reference clocks, and SERDES interfaces — the 100 MHz fundamental frequency feeds directly into a PLL or clock buffer without frequency multiplication.
Industrial temperature grade and deployment fit
The 6-VDFN package measures 3.20 mm x 2.50 mm with a seated height of 0.90 mm — a compact footprint that fits tight layout zones near the processor or FPGA.