125 MHz LVPECL clock source with MEMS reliability
The LVPECL output delivers the fast edge rates and low jitter needed for clocking high-speed ADCs, FPGAs, or SerDes transceivers — the 125 MHz frequency is a common reference for Gigabit Ethernet and 10G optical modules. For a 125 MHz clock, ±50 ppm translates to a maximum frequency error of ±6.25 kHz — sufficient for most non-PLL timing applications, but verify against your receiver's ppm capture range if the oscillator feeds a clock multiplier.
Supply range and disable function for power-sensitive designs
The supply voltage range of 2.25V to 3.63V covers common 2.5V and 3.3V rails without an external regulator. In a battery-powered design, gating the oscillator can save over half the clock-tree power.
6-VDFN package and board integration
Housed in a 6-VDFN package measuring 5.00 mm x 3.20 mm with a seated height of 0.90 mm, this oscillator fits standard 5.0 x 3.2 mm XO footprints. Surface-mount assembly with a 0.90 mm height keeps it compatible with mezzanine card spacing and low-profile enclosures.