130 MHz LVPECL clock source with MEMS reliability
The LVPECL output delivers the fast edge rates and low jitter required for high-speed clock distribution to FPGAs, SERDES, and 1 GbE PHYs. This stability budget is sufficient for most Ethernet reference clocks and FPGA transceiver PLLs without external VCXO trimming.
Supply voltage and power-down flexibility
The wide supply range (2.25V to 3.63V) lets the oscillator operate from a 2.5V or 3.3V rail without an intermediate LDO, simplifying the power tree and reducing BOM count.
Package and board-level integration
Housed in a 6-VDFN package measuring 3.20 mm × 2.50 mm with a seated height of 0.90 mm, the DSC1202CL3-130M0000T occupies minimal board area.