130 MHz LVPECL clock for industrial timing
The LVPECL output delivers the fast edge rates and low jitter needed for high-speed serial links, FPGA reference clocks, and SERDES interfaces.
Supply voltage spans 2.25V to 3.63V, covering 2.5V and 3.3V rails common in mixed-voltage designs. Typical active current is 50 mA at 130 MHz — the LVPECL output stage is the dominant draw, not the MEMS core.
Lifecycle status is listed as active. The 6-VDFN package (3.20 mm × 2.50 mm, 0.90 mm seated height) is a standard MEMS oscillator footprint, compatible with common reflow profiles.