64Kbit I²C EEPROM in a through-hole DIP-8
It communicates at up to 1 MHz on the bus, with a read access time of 400 ns. The wide supply range of 1.7V to 5.5V makes it suitable for mixed-voltage designs, from 1.8V logic to legacy 5V systems.
The 1 MHz clock frequency is the fast-mode-plus tier for I²C EEPROMs, allowing a 64Kbit read or write to complete in roughly 65 ms at full bus speed. The 400 ns access time is the delay from the slave address match to the first data byte appearing on SDA; this sets the minimum SCL high time and affects bus timing margin in multi-slave systems. For firmware, the 5 ms write-cycle time per page or word means the host must wait after each write command before polling the acknowledge — a standard I²C EEPROM handshake.
The ROHS3 compliance covers EU regulatory requirements for lead-free assembly.
Supply voltage: 1.7V to 5.5V — one part for multi-rail boards
The 1.7V minimum supply lets the EEPROM run directly from a single Li-ion cell (3.0V–4.2V) or a 1.8V logic rail without a separate regulator. The 5.5V maximum covers legacy 5V buses and industrial 5V-tolerant microcontrollers. This wide range simplifies BOM consolidation — one EEPROM line item serves multiple voltage domains across a product family.
