Parallel NOR flash for code shadowing and data storage
The S29GL128P90TFIR20: The 90 ns write cycle time (word/page) matches the read access, so page-program operations complete within the same timing window — useful when updating firmware in place without stalling the bus for extended periods.
Housed in a 56-TFSOP (0.724", 18.40 mm width) surface-mount package, supplied as the 56-TSOP variant. The parallel interface means the address and data buses are directly muxed to the host controller — no SPI serialization overhead. This is the same footprint used across the GL-P family, so a board layout for a 128Mbit part can accept a 256Mbit or 512Mbit sibling without a respin, provided the pinout is consistent within the series.
