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Infineon Technologies S29GL064S70TFA013 — Discrete Semiconductors

Infineon S29GL064S70TFA013 64Mbit NOR Flash, 70 ns, 56-TSOP

MPNS29GL064S70TFA013
End of Life

Infineon Technologies S29GL064S70TFA013, Automotive AEC-Q100 GL-S series, 64Mbit parallel NOR Flash, 70 ns access time, 2.7-3.6V, -40 to 85°C, 56-TSOP.

$5.05Ref. price · indicative, final on quote
Packaging56-TFSOP (0.724", 18.40mm Width)
StockContact for availability
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

S29GL064S70TFA013 Technical Specifications
ParameterValue
SeriesAutomotive, AEC-Q100, GL-S
Memory typeNon-Volatile
Mounting typeSurface Mount
Voltage2.7V ~ 3.6V
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageTape & Reel (TR); Cut Tape (CT)
TechnologyFLASH - NOR
Access time70 ns
Memory size64Mbit
Memory formatFLASH
Case56-TFSOP (0.724\", 18.40mm Width)
Memory organization8M x 8, 4M x 16
Write cycle time - word, page60ns

Product details

64 Mbit parallel NOR Flash for automotive and industrial control

The Infineon S29GL064S70TFA013 is a 64 Mbit parallel NOR Flash memory from the Automotive GL-S series, qualified to AEC-Q100 Grade 3 (-40 to +85 °C).

What the 70 ns access time and parallel interface mean for your design

The 70 ns access time sets the ceiling for random read latency from the memory array to the data bus. For a microcontroller executing code-in-place (XiP) from this NOR Flash, each instruction fetch adds 70 ns of wait-state overhead before the first data word appears on the parallel bus. The parallel interface (x8/x16) delivers the full memory bandwidth in a single cycle, unlike serial NOR which serializes the data over fewer pins. The 60 ns write cycle time (word/page) governs how fast the system can program the array. A page write completes in 60 ns after the data is latched, but the actual program operation inside the memory cell takes longer — the 60 ns figure is the bus cycle time, not the program time. Budget the full sector erase and program times from the datasheet's AC characteristics when sizing firmware update windows. No external regulator is needed if the system's 3.3 V rail stays within this window. At the low end (2.7 V), the access time may degrade slightly; the datasheet's AC timing is characterized across the full supply range.

This covers passenger cabin, infotainment, telematics, and ADAS sensor modules that do not see under-hood temperatures. The qualification includes reliability stress tests (HTOL, ESD, latch-up, temperature cycling) per the AEC-Q100 standard.

Package and board integration: 56-TSOP surface mount

Housed in a 56-TFSOP (0.724", 18.40 mm width) package, the supplier device package is 56-TSOP. This is a standard thin small-outline package with a 0.50 mm pin pitch, suitable for reflow soldering on standard FR-4 PCBs. The package is surface-mount only; no through-hole variant is available. The part is offered in Tape & Reel (TR) and Cut Tape (CT) options. The TR variant is intended for automated pick-and-place assembly lines; the CT option suits prototyping or low-volume builds where full reels are not justified.