512 Mbit NOR Flash with Quad-SPI for fast boot and code shadowing
It uses a SPI interface with Quad I/O support, allowing four-bit-wide data transfers that boost read throughput without adding pins. The 133 MHz clock rate translates to roughly 66 MB/s sustained read bandwidth in Quad mode — enough for fast boot, execute-in-place (XIP) code shadowing, or OTA staging in a connected device. Supply range is 2.7V to 3.6V, which aligns with common 3.3V logic rails.
At 133 MHz with Quad I/O, the S25FL512SAGMFIG13 delivers a read throughput that keeps a Cortex-M or RISC-V core fed during code execution from Flash. The SPI bus runs at 133 MHz, and with four data lines active each cycle, the effective data rate is 532 Mbps. That is enough to support 1080p video frame buffers or large lookup tables without waiting on a slower serial memory. The Quad I/O interface also reduces pin count compared to a parallel NOR, which simplifies PCB routing and frees up GPIOs on the host controller.
Package and footprint: 16-SOIC wide-body
That is a standard NOR Flash footprint shared across many 512 Mbit and 256 Mbit parts from Cypress and other vendors. The surface-mount package reflows with standard lead-free profiles;.