133 MHz clock and Quad I/O — what the throughput means for the bus
At 133 MHz in Quad I/O mode, the device delivers a sustained read throughput that keeps a Cortex-M or RISC-V core fed during execute-in-place (XIP) without stalling for flash wait states. The Quad-SPI interface uses four data lines, so the effective bandwidth is roughly four times that of a single-bit SPI at the same clock — useful for OTA update staging where a 32 MB firmware image needs to load quickly.
The FL-S series has broad distribution support, and the 16-SOIC footprint is a standard body width (7.50 mm) that reuses existing board layouts.
Package and storage note
Supplied in a Tray, surface-mount 16-SOIC (0.295" width, 7.50 mm).