256 Mbit NOR Flash in a 16-SOIC — SPI Quad I/O at 66 MHz
66 MHz clock — bus margin and throughput
At 66 MHz, the Quad I/O interface delivers a theoretical read throughput of 264 Mbps (66 MHz x 4 I/Os). That keeps the host controller's SPI peripheral from being the bottleneck in most embedded designs. The 66 MHz rating is the maximum clock; layout needs to keep trace lengths short and matched, especially if the SPI bus also drives a second device. The 256 Mbit density gives room for a bootloader, application image, and a small filesystem for configuration data.
The FL-L series has broad distribution support, so supply continuity looks solid for the next several years.