108 MHz Quad I/O — what the interface speed means for the bus
The 108 MHz SPI Quad I/O interface allows four data lines to transfer simultaneously, giving an effective read throughput that can keep a Cortex-M or similar core fed during code execution without wait-state penalties. For a firmware image up to 4 MB (the 4M × 8 organization), the page read time is fast enough for OTA staging, but the write cycle time of 3 ms per word/page means the programming throughput is modest — this is a NOR Flash, not a NAND, so it is chosen for reliable random-access read performance and fast boot, not bulk storage writes.