128 Mbit NOR Flash with Quad-SPI — what the 104 MHz clock buys you
In Quad I/O mode that gives a sustained read throughput that can keep a Cortex-M or RISC-V core fed without waiting on the flash — useful for execute-in-place (XIP) boot or OTA staging where the memory sits directly on the main bus.
Write-cycle timing is specified at 5 µs per word and 3 ms per page — relevant for firmware-update routines where the page-erase and program latency affects the OTA window.
