128 Mbit NOR Flash with Quad-SPI — what the 80 MHz clock buys you
At that clock rate, Quad-SPI read throughput is roughly 40 MB/s in fast-read quad-output mode — enough to support execute-in-place (XIP) for a microcontroller or FPGA configuration store without a separate DRAM cache.
16-SOIC footprint — layout and rework notes
The wide-body SOIC is easier to hand-rework than QFN or BGA alternatives — useful during prototyping or if a rework-lab tech needs to swap parts after a firmware revision.
