128 Mbit NOR Flash for firmware storage and code shadowing
The SPI Quad I/O interface at 80 MHz delivers a sustained read throughput of 320 Mbps — enough to shadow a boot image into RAM without stalling the host processor.
Housed in a 16-SOIC package (0.295-inch body width, 7.50 mm), the S25FL128SDSMFB001 uses the standard JEDEC SOIC-16 wide footprint. The 1.27 mm pin pitch is hand-solderable and rework-friendly — no hot-air nozzle alignment needed for a rework station.
Active lifecycle — no end-of-life clock running
Infineon lists this part as Active. No LTB notice, no successor announced.
