Quad I/O at 66 MHz — throughput and bus timing
Quad-SPI at 66 MHz gives a raw read throughput of roughly 33 MB/s in quad mode, which keeps a Cortex-M4 or similar MCU fed during firmware execution-in-place (XiP) without wait-state bottlenecks. The 66 MHz clock is the rated maximum; the actual throughput depends on the MCU's QSPI controller and the command overhead. For designs that need higher burst rates, the FL-S family includes 104 MHz variants, but the 66 MHz part is the cost-optimized choice for industrial temperature ranges.
The FL-S series has broad second-source coverage across the 128 Mbit density, so if a pin-compatible alternate is needed for dual-sourcing, the S25FL128SDPMFI003 (same die, different package) is a direct cross.