The S25FL128SDPBHVC03 is supplied in a 24-ball TBGA with a 8x6 mm body. The 0.80 mm ball pitch demands a controlled-impedance PCB stack-up for the SPI bus lines, especially at 66 MHz.
Memory density and interface
128 Mbit (16M x 8) of NOR Flash organized as 16M x 8 bits, accessed via a SPI Quad I/O interface at a clock frequency of 66 MHz. The Quad I/O mode allows four data lines to transfer simultaneously, quadrupling the read throughput over standard SPI without increasing the clock rate.
