The non-volatile storage holds firmware images, configuration tables, or calibration data that must survive power cycles.
133 MHz Quad SPI — throughput and bus timing
At 133 MHz with Quad I/O, the part can sustain read throughput well above what a single-bit SPI at lower clock rates delivers. That matters when the flash is used for execute-in-place (XIP) code or when loading FPGA bitstreams — the memory interface becomes the bottleneck, not the core. The Quad I/O protocol uses four data lines for reads, so the effective data rate is four bits per clock cycle.
Housed in a 16-SOIC package with a 7.50 mm body width (0.295" wide), the part is a surface-mount device that reflows with standard lead-free profiles.
Infineon lists the S25FL128SAGMFIG01 as Active (current production).
