The S25FL128LAGBHM023 communicates over a SPI interface with Quad I/O and QPI support, clocking at 133 MHz.
133 MHz Quad SPI — sustained read bandwidth for XIP and code shadowing
The 133 MHz clock frequency with Quad I/O mode delivers a sustained read throughput that supports execute-in-place (XIP) from the Flash, reducing the need for a separate DRAM or SRAM code shadow buffer. In designs where the host MCU or SoC boots directly from this NOR Flash, the Quad SPI interface minimizes latency during firmware startup and over-the-air update staging.
AEC-Q100 qualification covers temperature cycling, ESD, and latch-up stress tests for automotive use.
Supply range and package
It is housed in a 24-ball BGA (8x6 mm body), surface-mount package.