Asynchronous FIFO for 5 V legacy data paths
The CY7C429-15JXC is an 18K (2K x 9) asynchronous FIFO with 15 ns access time and 50 MHz data rate, operating from 4.5 V to 5.5 V.

Cypress CY7C429-15JXC, Series CY7C, asynchronous FIFO memory, 18K (2K x 9), 15 ns access time, 50 MHz data rate, 4.5 V–5.5 V supply, 0°C–70°C, 32-PLCC J-Lead, Tube.
| Parameter | Value |
|---|---|
| Series | CY7C |
| Mounting | Surface Mount |
| Expansion type | Depth, Width |
| Supply voltage | 4.5 V ~ 5.5 V |
| Current - supply | 65mA |
| Operating temperature | 0°C~70°C |
| Package | Tube |
| Function | Asynchronous |
| Data rate | 50MHz |
| Access time | 15ns |
| Memory size | 18K (2K x 9) |
| FWFT support | No |
| Case | 32-LCC (J-Lead) |
| Bus directional | Uni-Directional |
| Retransmit capability | Yes |
| Programmable flags support | No |
The CY7C429-15JXC is an 18K (2K x 9) asynchronous FIFO with 15 ns access time and 50 MHz data rate, operating from 4.5 V to 5.5 V.
No official pin-compatible successor or second-source alternate is recorded in the lifecycle documentation. A design revision to a newer 3.3 V FIFO with level shifters, or a CPLD-based FIFO implementation, would be the practical replacement path.
The memory is 18K bits organized as 2K x 9 (2,048 words of 9 bits each). The 9th bit is typically used for parity or a control flag alongside the 8-bit data byte.