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Infineon Technologies CY7C2565KV18-450BZI — Memory (DRAM / SRAM / Flash / EEPROM)

Cypress CY7C2565KV18-450BZI SRAM, 72Mbit QDR II+, 450 MHz, 165-FBGA

MPNCY7C2565KV18-450BZI
Obsolete

Cypress CY7C2565KV18-450BZI, SRAM - Synchronous QDR II+, 72Mbit (2M x 36), 450 MHz clock, parallel interface, 1.7V-1.9V supply, -40°C to 85°C, 165-FBGA (13x15), Tray.

$577.5100Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C2565KV18-450BZI specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage1.7V ~ 1.9V
Clock frequency450 MHz
Memory interfaceParallel
Operating temperature-40°C~85°C(TA)
PackageTray
TechnologySRAM - Synchronous, QDR II+
Memory size72Mbit
Memory formatSRAM
Case165-LBGA
Memory organization2M x 36

Product details

QDR II+ vs QDR II — the bus-turnaround difference

QDR II+ adds a separate read and write data port, each clocked at the same frequency, so the controller never has to turn the bus around between read and write cycles. On a standard QDR II part, the address bus is shared and requires a dead cycle to switch direction.

Obsolete — sourcing reality for the BOM line

Frequently asked questions

Is CY7C2565KV18-450BZI obsolete?

Yes, Cypress has classified the CY7C2565KV18-450BZI as Obsolete. No official replacement part number has been published.

Where can I buy CY7C2565KV18-450BZI?

This obsolete part is sourced to order against an RFQ through independent distribution. Availability and current pricing are confirmed at quote time — submit an RFQ for a firm position.

What are the specs of CY7C2565KV18-450BZI?

72Mbit synchronous QDR II+ SRAM organized 2M x 36, 450 MHz clock, parallel interface, 1.7V to 1.9V supply, -40°C to 85°C operating temperature, 165-FBGA (13x15) package.

What is the difference between QDR II+ and QDR II SRAM?

QDR II+ uses separate read and write data ports, each clocked at the same frequency, eliminating the bus-turnaround dead cycle that QDR II incurs when switching between read and write on a shared address bus. This sustains full throughput in alternating read/write patterns.