It clocks at 500 MHz on the parallel interface, delivering back-to-back read and write transactions without bus-turnaround dead cycles — the defining advantage of the QDR II+ family for high-throughput buffer applications in networking, telecom line cards, and test equipment. Supply range is 1.7 V to 1.9 V, and the part is housed in a 165-ball FBGA (13x15 mm footprint).
The 500 MHz clock rate on this QDR II+ device enables double-data-rate transfers on both read and write ports.
This part carries an end-of-life (hot) lifecycle stage.
