256Kbit asynchronous SRAM — 12 ns access, 5V parallel interface
The CY7C199CN-12ZXC is a 256Kbit asynchronous SRAM organized as 32K x 8 bits, with a 12 ns access time that sets the read-cycle floor for the bus master. Packaged in a 28-TSOP I (0.465" body width, 11.80 mm), the surface-mount footprint is common for mid-density SRAMs and routes directly to a standard 28-pin TSOP layout.
