Legacy 5 V bus buffer — 15 ns read cycle
The CY7C199CL-15ZXC is a 256 Kbit asynchronous SRAM organised as 32K x 8, with a 15 ns access time that sets the minimum read-cycle window for the host bus. The 15 ns write cycle time (word, page) matches the read access, so the bus timing is symmetric — no wait-state penalty on writes that the read side does not also see.
Supplied in a 28-TSSOP (0.465", 11.80 mm width) body, the supplier device package is 28-TSOP I — a standard thin small-outline package with a 0.55 mm lead pitch.
Infineon lists this part as Obsolete. Sourcing is through independent distribution; quantities are lot-specific and confirmed at RFQ.