12 ns asynchronous SRAM — 256Kbit in a 28-SOJ footprint
The CY7C199C-12VI is a 256Kbit asynchronous SRAM organized as 32K x 8, with a 12 ns access time that sets the read-cycle ceiling for the memory bus. The 4.5V to 5.5V supply rail keeps it in single-5V systems without a separate core voltage. The 28-SOJ package (0.300-inch body width) is a surface-mount footprint that mates with standard SOJ sockets or direct-solder pads.
No pin-compatible direct replacement from Infineon is documented, so a board spin may be required if a functional equivalent is needed.
