64Kbit asynchronous SRAM, 20 ns access
The CY7C185-20VC is a 64Kbit asynchronous SRAM organized as 8K x 8, with a 20 ns access time that sets the read-cycle floor for the bus it connects to. The parallel memory interface and 20 ns write cycle time (word, page) mean the part can keep up with a 50 MHz bus without wait states, provided the controller's output hold times are met.
